The present disclosure relates to semiconductor devices each including an interlayer dielectric having pores, and methods for fabricating the same.
With miniaturization of semiconductor devices and an increase in the integration density thereof, a decrease in the propagation speed of an electrical signal due to an increase in interconnect resistance and an increase in interconnect capacitance have become a more serious problem.
In particular, in a highly integrated semiconductor device, an increase in interconnect capacitance leads to a decrease in the operation speed of the semiconductor device, thereby suppressing the increase in interconnect capacitance by using a material having a low dielectric constant for an interlayer dielectric, i.e., by using a low-dielectric-constant interlayer dielectric. Moreover, in recent years, development and practical use of a material of which the dielectric constant is reduced by making SiOC, etc., porous have been also studied.
A conventional semiconductor device using a low-dielectric-constant interlayer dielectric (see Japanese Patent Publication No. 2007-250706) will be described below with reference to FIG. 6. In the conventional semiconductor device, films having different properties are used, e.g., as an insulating film (interconnect layer insulating film) in which an interconnect is formed, and an insulating film (via layer insulating film) in which a via is formed.
Specifically, as illustrated in FIG. 6, a first insulating film 12 having pores is formed on a substrate 11, and then a second insulating film 13 having pores is formed on the first insulating film 12. Here, the material and deposition conditions of the second insulating film 13 are selected so that the carbon content of the second insulating film 13 is greater than that of the first insulating film 12. Next, an interlayer dielectric obtained by stacking the first and second insulating films 12 and 13 having different carbon contents is subjected to fabrication processes, such as lithography, dry etching, ashing, and cleaning, thereby forming a via hole 14 and an interconnect trench 15 in the first insulating film 12 and the second insulating film 13, respectively, as illustrated in FIG. 6. Next, although not shown, an interconnect structure including an interconnect and a via is formed by embedding a metal, such as Cu, in the interconnect trench 15 and the via hole 14.
The above-described conventional interlayer dielectric configuration described in Japanese Patent Publication No. 2007-250706 has a hybrid structure obtained by stacking two insulating films having different carbon contents, and one of the features of the conventional interlayer dielectric configuration is that the carbon content of the interconnect layer insulating film (the second insulating film 13) is greater than that of the via layer insulating film (the first insulating film 12). Typically, with an increase in the carbon content of an insulating film, the etch rate thereof tends to be higher. Therefore, when the interconnect layer insulating film is etched, i.e., when the interconnect trench is formed by etching, the method described in Japanese Patent Publication No. 2007-250706 can increase the etch selectivity to the via layer insulating film. This allows the depth of the interconnect trench to be uniform, and enables the fabrication of a semiconductor device having an interconnect structure with a small variation in interconnect resistance.